CPU architecture and the fetch–decode–execute cycle
Explain CPU components, buses, registers, the Von Neumann architecture and the limits of simple performance comparisons.
Mapped to the Cambridge IGCSE Computer Science 0265 syllabus for exams in 2029. These original explanations and self-checks are independent study support, not Cambridge papers, official marks or grades. Practical programming is taught with worked code and trace tasks; an executable Python workspace and timed digital-exam simulation are not yet available.
Before you begin
- Use the 2029 syllabus for this course. Cambridge specifies Python 3.10 or higher for programming and digital exams for both components. The syllabus currently identifies this route for 2029 only; confirm later-year availability with Cambridge and your school.
Work on paper. Try each question before revealing help, and explain why your method works.
Quick readiness check
Before cpu architecture and the fetch–decode–execute cycle, which statement is the safest starting point?
What you will learn
- Describe the CPU and microprocessor
- Explain the roles of CPU components and buses
- Trace the fetch–decode–execute cycle and factors affecting performance
The CPU coordinates processing
The central processing unit (CPU) executes program instructions. A microprocessor is a CPU implemented as an integrated circuit on one chip. In the Von Neumann architecture, instructions and data share main memory, and the CPU retrieves and processes them.
The control unit (CU) coordinates operations; the arithmetic logic unit (ALU) performs arithmetic and logic. The program counter (PC) stores the next instruction address, the memory address register (MAR) holds an address being accessed, the memory data register (MDR) holds data moving to or from memory, the current instruction register (CIR) holds the instruction being handled, and the accumulator (ACC) stores intermediate results.
FDE moves addresses, data and control
During fetch, the address in the PC is copied to the MAR and sent along the address bus. Memory returns the instruction through the data bus into the MDR; it is copied to the CIR and the PC advances. During decode, the CU interprets the instruction. During execute, the CU, ALU, registers and memory carry out the instruction using control signals on the control bus.
More cores can allow more work to run concurrently when software supports it; larger cache can keep frequently needed data closer to the CPU; a higher clock speed can execute more clock cycles per second. None alone guarantees a faster system because workload, architecture, memory and software also matter. The instruction set defines machine instructions a CPU can execute.
Pause and explain
Which habit best checks your understanding of cpu architecture and the fetch–decode–execute cycle?
Worked example
Which register holds the address of the next instruction before it is fetched?
Show the worked solution
- The CPU needs a location to identify the next instruction.
- The PC stores that address.
- The MAR receives the address for a memory access.
Answer The PC holds it first; it is copied to the MAR during fetch.
Try a topic test
Choose Easy, Normal or Difficult. Save your answers and open worked review after finishing.
Test this topic →From guided practice to a new situation
Write your answer and reasoning first. Use a hint only if you are stuck. The model solution is for self-checking; your written work is not automatically marked.
A CPU fetches an instruction from address 240. Trace the roles of PC, MAR, MDR and CIR.
Give me a hint
Separate the instruction address from the instruction's contents.
Compare my reasoning
- PC contains 240, the next instruction address.
- The address is copied into MAR; memory sends the stored instruction via MDR.
- The instruction is copied into CIR for decoding; PC is updated for the next fetch.
PC → MAR → memory/MDR → CIR; PC then advances.
Look for these in your work
- Address source named
- Transfer registers ordered
- PC update included
Explain the role of each bus when the CPU reads a value from memory.
Give me a hint
Ask what travels on each bus and in which direction the data moves.
Compare my reasoning
- The address bus carries the location from CPU toward memory.
- The control bus carries the read command and timing/control signals.
- The data bus carries the value from memory back to the CPU, commonly through the MDR.
Address bus identifies the location; control bus coordinates the read; data bus carries the value.
Look for these in your work
- Address role
- Control role
- Data flow
A video-editing computer has a larger cache but the same number of cores and clock speed. Explain one way this could help and why it may not always improve the task.
Give me a hint
Connect cache to access time, then name a condition that limits the benefit.
Compare my reasoning
- Frequently reused instructions or data may be found in cache rather than slower main memory.
- That can reduce waiting and improve performance for suitable workloads.
- If the task does not reuse cached data or another component is the bottleneck, the improvement may be small.
A larger cache can help repeated data access, but benefits depend on workload and other bottlenecks.
Look for these in your work
- Mechanism described
- Workload link made
- Limitation stated
Common mistakes
- Saying the MAR holds the instruction rather than its address.
- Treating the data bus and address bus as interchangeable.
- Assuming clock speed alone determines computer performance.
What can you explain now?
Which register stores the instruction currently being decoded?
Compare with the explanation
CIR
The current instruction register holds the fetched instruction for decoding and execution.
After trying it yourself, choose your next review. This is your self-assessment.
Your review choice appears on Today. Sign in to sync it across devices.
Make it stick
Which CPU registers and buses participate in fetching an instruction, and what affects CPU performance?
If you needed the solution, close it and solve the problem again from a blank page. A correct answer is stronger when you can explain the reason for each step.