4 Processor fundamentals
Trace how a stored-program processor fetches and executes instructions, then read simple assembly operations and bit masks.
Mapped to Cambridge International AS & A Level Computer Science 9618, 2027–2029 Version 2. These original lessons and self-checks are independent study support; they are not Cambridge papers, official marks or grades. The course does not yet provide a timed four-paper simulation or a locked-down Paper 4 programming environment.
Before you begin
- Use the 2027–2029 syllabus for your exam year. AS candidates study Sections 1–12; A Level candidates study Sections 1–20. Paper 4 uses a programming language chosen from Python, Java or Visual Basic in console mode.
Work on paper. Try each question before revealing help, and explain why your method works.
Quick readiness check
Which register holds the address for a memory access?
What you will learn
- Explain the key representations, structures or processes in this syllabus section
- Apply the method to a new computer-science example
- Justify a design choice and check its limits
The CPU moves addresses, instructions and data
The Von Neumann model stores program instructions and data in memory. The program counter (PC) identifies the next instruction; MAR holds a memory address, MDR holds data transferred, CIR holds the current instruction and ACC stores arithmetic or logic results. The address, data and control buses have different roles.
During fetch–decode–execute, the address in PC is copied to MAR, memory returns the instruction via MDR, and it is placed in CIR. The PC advances; the control unit decodes the instruction and directs its execution. A branch can replace the next address.
General-purpose registers hold data for many operations; special-purpose registers have defined processor roles. Exact internal timing depends on the model used in a question.
Assembly names low-level operations
An instruction has an operation code and may include an operand. Immediate addressing uses a literal value; direct addressing uses a stated address; indirect addressing follows an address stored at another location; indexed addressing adds an index to a base; relative addressing offsets the current program location.
Bitwise shifts move bits within a fixed-width value. A logical shift inserts zeros; a rotate moves bits that leave one end back to the other. AND, OR and XOR masks can test, set or toggle selected bits. Track the stated width because discarded bits cannot be assumed to return.
Pause and explain
What does bitwise AND with a mask commonly do?
Worked example
An 8-bit value is 00101100. Apply the mask 00001111 using bitwise AND.
Show the worked solution
- Compare each bit position.
- AND gives 1 only where both corresponding bits are 1.
- The low four bits remain; the high four positions become 0.
Answer 00001100.
Try a topic test
Choose Easy, Normal or Difficult. Save your answers and open worked review after finishing.
Test this topic →From guided practice to a new situation
Write your answer and reasoning first. Use a hint only if you are stuck. The model solution is for self-checking; your written work is not automatically marked.
In a fetch cycle, PC contains address 512. Which register receives 512 for the memory access, and where does the fetched instruction travel before decoding?
Give me a hint
Separate the address path from the data path.
Compare my reasoning
- Copy the address from PC to MAR.
- Memory returns the instruction through MDR.
- The instruction is then loaded into CIR for decoding.
MAR receives 512; the instruction travels through MDR to CIR.
Look for these in your work
- Address register correct
- Data register correct
- Decode register correct
A processor instruction uses immediate addressing to add the value 7 to ACC. Does 7 name a memory location or the value to use? Explain.
Give me a hint
The word immediate distinguishes a literal operand from an address.
Compare my reasoning
- Immediate addressing uses the operand itself.
- So 7 is the literal value, not the address to dereference.
- The operation adds that value to the accumulator.
7 is the value to use directly.
Look for these in your work
- Literal identified
- Address distinction made
- Operation linked
An 8-bit register contains 10110001. Rotate it right by one bit. Show the result and explain what happens to the bit that leaves the right edge.
Give me a hint
Unlike a logical shift, a rotate wraps the outgoing bit to the opposite end.
Compare my reasoning
- The rightmost bit is 1.
- Move the other bits one position right.
- Place the outgoing 1 in the leftmost position.
11011000; the outgoing rightmost 1 wraps to the leftmost position.
Look for these in your work
- Width retained
- Bits moved correctly
- Wrap-around explained
Common mistakes
- Confusing the address in MAR with the value in MDR.
- Treating immediate data as a memory address.
- Assuming a shift and a rotate discard bits in the same way.
What can you explain now?
Which register normally identifies the next instruction to fetch?
Compare with the explanation
The program counter (PC)
PC contains the address for the next fetch; MAR is used for a particular memory access.
After trying it yourself, choose your next review. This is your self-assessment.
Your review choice appears on Today. Sign in to sync it across devices.
Make it stick
During fetch–decode–execute, which registers hold the next address, memory address, transferred data and current instruction?
If you needed the solution, close it and solve the problem again from a blank page. A correct answer is stronger when you can explain the reason for each step.