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A Level · Cambridge (CIE) · 9618

Registers and the fetch cycle

Distinguish an instruction's address, its contents and the CPU's working data.

What you will learn

  • Explain the roles of PC, MAR, MDR and CIR.
  • Outline a fetch sequence.

Registers hold different kinds of information

The program counter holds the address of the next instruction to fetch. The memory address register holds the address used for a memory access. The memory data register holds data being transferred to or from memory. The current instruction register holds the instruction being decoded or executed.

An accumulator is a working register used for intermediate arithmetic or logic results in some processor models. It does not replace the program counter.

Follow the information flow

In a simplified fetch cycle, the next instruction address is copied from the PC to the MAR. Memory returns the instruction through the MDR, and the instruction is placed in the CIR. The PC is updated so execution can continue; a branch may later change its value.

Exact micro-operation ordering depends on the processor model. The transferable skill is knowing which register stores an address and which stores the contents at that address.

Put the idea to work

Worked example

The next instruction is at address 240. Which register holds 240 before the fetch begins, and which register receives that address for the memory access?

Show the worked solution
  1. Before fetching, the PC identifies the next instruction address.
  2. That address is copied to the MAR for the memory operation.
  3. The instruction stored at address 240 is separate from the number 240.

Answer PC first, then MAR

Common mistakes

  • An address is not the instruction stored there.
  • The CIR stores the current instruction, not the next instruction's address.
Recall without your notes

What can you explain now?

Which register temporarily holds data arriving from memory?

Compare with the explanation

MDR

The memory data register carries the contents being transferred, whereas the MAR identifies a location.

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Course scope and assessment

This pathway maps the 2026 Version 2 and 2027–2029 Version 2 syllabuses, which Cambridge says have no significant changes affecting teaching. It has original teaching and guided, independent and transfer practice for all 20 syllabus sections, with topic links to the official section headings. It is mapped teaching, not proof of exam readiness or an official Cambridge grade. Paper 4 requires complete programs and testing evidence in a programming environment; the current course offers explained code and algorithm practice but does not yet provide a locked-down timed programming-paper environment, full four-paper mocks or human subject-teacher review.

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