Trace the fetch–decode–execute cycle
Follow an instruction from RAM through the CPU registers, control unit and ALU.
Exam scope and assessment notes
This sequence follows Cambridge IGCSE Computer Science 0984, 2026–2028 syllabus Version 4. It covers subject content sections 3.1–3.3 only. The separately published 2029–2031 syllabus is not mapped here. Practice is original, self-checked and does not award an official Cambridge grade. Full timed papers and human subject-teacher review remain outstanding. Cambridge states that 0984 has the same 2026–2028 subject content as 0478, with 9–1 grading. In June and November, Cambridge lists 0984 in Administrative zone 3 and for centres in Oman and the UAE. Confirm availability for your centre and exam series with Cambridge International. The separately published 2029–2031 syllabus changes to Python 3 only and removes pseudocode; this 2026–2028 route does not cover those changes.
Before you begin
- No programming language is required. Be comfortable with place value and multiplication; each lesson introduces the computer-science notation it uses.
Work on paper. Try each question before revealing help, and explain why your method works.
Quick readiness check
Where is the next instruction stored before it is fetched?
What you will learn
- Describe instruction fetch from RAM
- Explain decoding and execution
- Connect registers and buses to their roles in the cycle
Fetch brings an instruction into the CPU
The PC contains the next instruction's address. That address is copied to the MAR and sent over the address bus with a read signal. The instruction is returned on the data bus through the MDR and copied into the CIR. The PC is updated to the following instruction address.
Apply and check the rule
During decode, the control unit interprets the instruction and coordinates the required signals. During execute, the ALU or another component performs the operation; data may move through the ACC and results may be stored. A branch instruction can alter the next PC value.
Pause and explain
During fetch, what is copied from the MDR to the CIR?
Worked example
An instruction at address 120 adds two values. Outline the stages.
Show the worked solution
- Fetch the instruction at address 120 into the CIR using PC, MAR, MDR and the buses.
- The CU decodes the instruction and identifies the operation and operands.
- The ALU adds the values; the result can be held in the ACC or stored as instructed.
Answer Fetch the instruction, decode it in the CU, then execute the addition in the ALU and store the result.
Try a topic test
Choose Easy, Normal or Difficult. Save your answers and open worked review after finishing.
Test this topic →From guided practice to a new situation
Write your answer and reasoning first. Use a hint only if you are stuck. The model solution is for self-checking; your written work is not automatically marked.
Put these roles in order for instruction fetch: CIR, PC, MDR, MAR.
Give me a hint
Start with the next address, then the memory access and returned instruction.
Compare my reasoning
- PC identifies the address.
- MAR receives the address; MDR receives the instruction from memory.
- CIR stores the current instruction.
PC → MAR → MDR → CIR
Look for these in your work
- Address source
- Memory transfer
- Instruction register
An instruction says to add values held in two registers. Which CPU component performs the addition?
Give me a hint
Decode identifies the operation; execution performs it.
Compare my reasoning
- The control unit decodes and coordinates.
- The ALU performs the arithmetic operation.
The ALU
Look for these in your work
- CU role separated
- ALU selected
The PC normally advances after fetching an instruction, but a conditional branch is taken. Explain what changes about the next fetch.
Give me a hint
The branch can change which address the PC identifies.
Compare my reasoning
- A normal fetch updates the PC to the next sequential address.
- A taken branch supplies a different target address.
- The next fetch uses the updated PC, so it reads from the branch target.
The branch changes the PC to the target address. The next instruction is fetched from that address rather than the next sequential location.
Look for these in your work
- Normal update stated
- Branch target identified
- Effect on next fetch
Common mistakes
- Putting the data value in the PC
- Saying the CU performs the arithmetic instead of coordinating it
What can you explain now?
Which unit decodes the current instruction?
Compare with the explanation
Control unit
The control unit interprets the instruction and coordinates the signals needed for execution.
After trying it yourself, choose your next review. This is your self-assessment.
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Make it stick
What information does each of the PC, MAR, MDR and CIR hold during a fetch?
If you needed the solution, close it and solve the problem again from a blank page. A correct answer is stronger when you can explain the reason for each step.